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How to make Adder in VHDL?

By Applied Electronics - Friday, April 17, 2015 No Comments
There are couple of ways in which one can write an adder circuit in VHDL. One way is to utilize the '+' operator in VHDL.

Here we shows how to make an adder in VHDL using the + operator defined in the std_logic_unsigned package.

The  std_logic_unsigned package allows one to add std_logic signals using the '+' operator. Consider the following simple code of adder in VHDL which adds two 16 bit numbers a and b and f is the sum.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity myadder is
    port(
    x, y : in std_logic_vector(7 downto 0);
    f : out std_logic_vector(7 downto 0)
    );
end myadder;

architecture model of myadder is
begin
        f <= x + y;
end model;

Here the package std_logic_unsigned of the ieee library has been used. This is a simple adder in VHDL using the '+' operator.

Usually, an adder circuit has carry input from previous calculation and it also has carrry out which is the overflow of the addition of two numbers.

Below is a code that includes carry input and carry output.


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity myadder is
    port(
    x, y : in std_logic_vector(7 downto 0);
    cin : in std_logic;
    sum : out std_logic_vector(7 downto 0);
    cout : out std_logic
    );
end myadder;

architecture model of myadder is
signal f : std_logic_vector(8 downto 0);
signal z : std_logic_vector(8 downto 0);
begin
    z <= '0'&x;
    f <= z + y + cin;
    sum <= f(7 downto 0);
    cout <=    f(8);
end model;

We use concatenation operator & to concatenate
Now we can verify that when there is overflow that the carry output is 1 using a VHDL CAD software as shown below.



In this way we can easily design an adder in VHDL using the + mathematical operator using the std_logic_unsigned operator.

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